As a technique to manufacture a wiring substrate of a multilayer structure, a build-up method has heretofore been widely used. In recent years, in order to achieve a thinner wiring substrate, a wiring substrate having a structure without a core substrate (also called “coreless substrate”) has been employed.
However, the thin substrate such as coreless substrate or the like as above is low in rigidity as a whole due to the absence of a core part and therefore has a problem that warpage is likely to occur. Warpage appears significantly especially when a semiconductor element (typically, a silicon chip) is mounted by performing reflow soldering for connecting the terminals between the chip and substrate, and when the underfill resin is filled under the semiconductor element, and also when the secondary mounting is performed, that is, the substrate equipped with the chip is mounted onto a motherboard or the like by performing reflow soldering. This is because a considerable amount of heat is applied to the substrate when these processes are performed.
On the other hand, due to increase in integration density of semiconductor element and improvement in functionality thereof, the wiring substrate for mounting the semiconductor element has been required to have finer and denser wirings accordingly. An organic resin is mainly used as the base material of such a wiring substrate. However, a substrate using an organic resin does not have a flat surface and thus has a limitation to make the wiring respond to the finer fabrication.
To solve this, a structure in which a semiconductor element is mounted on a wiring substrate through a silicon interposer which is capable of the finer fabrication, has been proposed.
As the technique related to such a conventional technique, as described in Patent Document 1 (Japanese Laid-open Patent Publication No. 2009-130104), for example, there is a substrate structure in which an interposer is connected to a coreless substrate through vias. As another technique, as described in Patent Document 2 (Japanese Laid-open Patent Publication No. 2010-239126), also there is a structure in which an interposer is incorporated in a coreless substrate.
As mentioned above, the thin substrate such as conventional coreless substrate, or the like is low in rigidity as a whole and therefore has the problem that warpage is likely to occur when a semiconductor element is mounted thereon, or the like. To solve this, various measures have heretofore been taken.
However, the elastic modulus and coefficient of thermal expansion (CTE) as a whole of the wiring substrate having an organic resin as its base material, are far different from the elastic modulus and CTE of a semiconductor element (whose base material is silicon) mounted thereon. Thus, it is a present condition that a sufficient measure can not be taken against the warpage.